A custom accelerator for homomorphic encryption applications
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Date
2017
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE Computer Society
Access Rights
info:eu-repo/semantics/closedAccess
Abstract
After the introduction of first fully homomorphic encryption scheme in 2009, numerous research work has been published aiming at making fully homomorphic encryption practical for daily use. The first fully functional scheme and a few others that have been introduced has been proven difficult to be utilized in practical applications, due to efficiency reasons. Here, we propose a custom hardware accelerator, which is optimized for a class of reconfigurable logic, for López-Alt, Tromer and Vaikuntanathan's somewhat homomorphic encryption based schemes. Our design is working as a co-processor which enables the operating system to offload the most compute-heavy operations to this specialized hardware. The core of our design is an efficient hardware implementation of a polynomial multiplier as it is the most compute-heavy operation of our target scheme. The presented architecture can compute the product of very-large polynomials in under 6.25 ms which is 102 times faster than its software implementation. In case of accelerating homomorphic applications; we estimate the per block homomorphic AES as 442 ms which is 28.5 and 17 times faster than the CPU and GPU implementations, respectively. In evaluation of Prince block cipher homomorphically, we estimate the performance as 52 ms which is 66 times faster than the CPU implementation. © 1968-2012 IEEE.
Description
Keywords
accelerator for homomorphic encryption, FPGA, NTT multiplication, Somewhat homomorphic encryption
Journal or Series
IEEE Transactions on Computers
WoS Q Value
Q1
Scopus Q Value
Q1
Volume
66
Issue
1
