Evaluating the hardware performance of a million-bit multiplier

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dc.contributor.authorDoroz, Yarkın
dc.contributor.authorÖztürk, Erdinç
dc.contributor.authorSunar, Berk
dc.date.accessioned2020-11-21T15:56:37Z
dc.date.available2020-11-21T15:56:37Z
dc.date.issued2013en_US
dc.departmentİstanbul Ticaret Üniversitesien_US
dc.description16th Euromicro Conference on Digital System Design, DSD 2013 -- 4 September 2013 through 6 September 2013 -- Santander -- 101116en_US
dc.description.abstractIn this work we present the first full and complete evaluation of a very large multiplication scheme in custom hardware. We designed a novel architecture to realize a million-bit multiplication architecture based on the Schönhage-Strassen Algorithm and the Number Theoretical Transform (NTT). The construction makes use of an innovative cache architecture along with processing elements customized to match the computation and access patterns of the FFT-based recursive multiplication algorithm. When synthesized using a 90nm TSMC library operating at a frequency of 666 MHz, our architecture is able to compute the product of integers in excess of a million bits in 7.74 milliseconds. Estimates show that the performance of our design matches that of previously reported software implementations on a high-end 3 Ghz Intel Xeon processor, while requiring only a tiny fraction of the area. © 2013 IEEE.en_US
dc.identifier.doi10.1109/DSD.2013.108en_US
dc.identifier.endpage962en_US
dc.identifier.isbn9780770000000
dc.identifier.scopus2-s2.0-84890074079en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.startpage955en_US
dc.identifier.urihttps://doi.org/10.1109/DSD.2013.108
dc.identifier.urihttps://hdl.handle.net/11467/4158
dc.identifier.wosWOS:000337235200130en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.relation.ispartofProceedings - 16th Euromicro Conference on Digital System Design, DSD 2013en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectFFTen_US
dc.subjectHomomorphic encryptionen_US
dc.subjectLarge multiplieren_US
dc.subjectNumber theoretical transformen_US
dc.titleEvaluating the hardware performance of a million-bit multiplieren_US
dc.typeConference Objecten_US

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