Design and Implementation of a Constant-time FPGA Accelerator for Fast Elliptic Curve Cryptography
| dc.contributor.author | Ay, Atil U. | |
| dc.contributor.author | Ozturk, Erdinc | |
| dc.contributor.author | Henriquez, Francisco Rodriguez | |
| dc.contributor.author | Savas, Erkay | |
| dc.date.accessioned | 2024-10-12T19:42:54Z | |
| dc.date.available | 2024-10-12T19:42:54Z | |
| dc.date.issued | 2016 | |
| dc.department | İstanbul Ticaret Üniversitesi | en_US |
| dc.description | International Conference on Reconfigurable Computing and FPGAs (ReConFig) -- NOV 30-DEC 02, 2016 -- Cancun, MEXICO | en_US |
| dc.description.abstract | In this paper we present a scalar multiplication hardware architecture that computes a constant-time variable-base point multiplication over the Galbraith-Lin-Scott (GLS) family of binary elliptic curves. Our hardware design is especially tailored for the quadratic extension field F-22n ; with n = 127; which allows us to attain a security level close to 128 bits. We explore extensively the usage of digit-based and Karatsuba multipliers for performing the quadratic field arithmetic associated to GLS elliptic curves and report the area and time performance obtained by these two types of multipliers. Targeting a XILINX KINTEX-7 FPGA device, we report a hardware implementation of our design that achieves a delay of just 3.98 mu s for computing one scalar multiplication. This allows us to claim the current speed record for this operation at or around the 128-bit security level for any hardware or software realization reported in the literature. | en_US |
| dc.description.sponsorship | Natl Inst Astrophys Opt & Elect Mexico,Virginia Tech,Univ N Carolina Charlotte,IEEE Circuits & Syst Soc,XILINX | en_US |
| dc.identifier.isbn | 978-1-5090-3707-0 | |
| dc.identifier.issn | 2325-6532 | |
| dc.identifier.uri | https://hdl.handle.net/11467/8644 | |
| dc.identifier.wos | WOS:000400775800021 | en_US |
| dc.identifier.wosquality | N/A | en_US |
| dc.indekslendigikaynak | Web of Science | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.relation.ispartof | 2016 International Conference On Reconfigurable Computing And Fpgas (Reconfig16) | en_US |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.snmz | WoS_2024 | en_US |
| dc.title | Design and Implementation of a Constant-time FPGA Accelerator for Fast Elliptic Curve Cryptography | en_US |
| dc.type | Conference Object | en_US |
