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Design and implementation of a constant-Time FPGA accelerator for fast elliptic curve cryptography
(Institute of Electrical and Electronics Engineers Inc., 2016) Ay, Atıl U.; Öztürk, Erdinç; Henriquez, F.R.; Savaş, Ekrem
In this paper we present a scalar multiplication hardware architecture that computes a constant-Time variable-base point multiplication over the Galbraith-Lin-Scott (GLS) family of binary elliptic curves. Our hardware design is especially tailored for the quadratic extension field F22n, with n = 127, which allows us to attain a security level close to 128 bits. We explore extensively the usage of digit-based and Karatsuba multipliers for performing the quadratic field arithmetic associated to GLS elliptic curves and report the area and time performance obtained by these two types of multipliers. Targeting a XILINX KINTEX-7 FPGA device, we report a hardware implementation of our design that achieves a delay of just 3.98?s for computing one scalar multiplication. This allows us to claim the current speed record for this operation at or around the 128-bit security level for any hardware or software realization reported in the literature. © 2016 IEEE.