Ay, Atıl U.Öztürk, ErdinçHenriquez, F.R.Savaş, Ekrem2020-11-212020-11-2120169781510000000https://doi.org/10.1109/ReConFig.2016.7857163https://hdl.handle.net/11467/41272016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 -- 30 November 2016 through 2 December 2016 -- -- 126407In this paper we present a scalar multiplication hardware architecture that computes a constant-Time variable-base point multiplication over the Galbraith-Lin-Scott (GLS) family of binary elliptic curves. Our hardware design is especially tailored for the quadratic extension field F22n, with n = 127, which allows us to attain a security level close to 128 bits. We explore extensively the usage of digit-based and Karatsuba multipliers for performing the quadratic field arithmetic associated to GLS elliptic curves and report the area and time performance obtained by these two types of multipliers. Targeting a XILINX KINTEX-7 FPGA device, we report a hardware implementation of our design that achieves a delay of just 3.98?s for computing one scalar multiplication. This allows us to claim the current speed record for this operation at or around the 128-bit security level for any hardware or software realization reported in the literature. © 2016 IEEE.eninfo:eu-repo/semantics/closedAccessConference ObjectN/A2-s2.0-8501509488510.1109/ReConFig.2016.7857163